The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology which is effective in application to a static RAM (Random Access Memory) having a Bi-CMOS structure (i.e., a compound circuit of bipolar type transistors and a CMOS (Complementary Metal Oxide Semiconductor) circuit) having an ECL (Emitter Coupled Logic) interface.
There is a static RAM having the Bi-CMOS structure (Complementary Metal Oxide Semiconductor) which uses an ECL circuit as its input/output circuit while aiming at a high density and a power reduction by using memory cells comprising complementary metal oxide semiconductor field effect transistors (hereinafter referred to as CMOS circuits). A static RAM of this Bi-CMOS structure is described on pp. 32-33 and 281 of ISSCC Digest of Technical Papers, February 1989. This static RAM requires a level converter for converting an ECL level to a CMOS level. A high speed is intended in a device disclosed in Japanese Patent Laid-Open No. 152798/1991 by omitting the level converter. Another ECL-CMOS level converter is also disclosed in Japanese Patent Laid-open No. 276385/ 1992, laid-open on Oct. 1, 1992 (corresponding to U.S. patent application Ser. No. 07/845,557, filed on Mar. 4, 1992), now U.S. Pat. No. 4,255,225.